This document describes the STA0500A 4kx4k CCD in its backside version.  The device was designed by Richard Bredthauer (Semiconductor Technology Associates, Inc) and is backside processed in out lab.

Architecture:

•  4063 columns
•  4060 rows
•  15 x 15 micron square pixels
•  2 pre-scan pixels before each amplifier
•  4 amplifiers
•  MPP or normal operation
•  MPP barrier phase: P3
•  Split imaging area to allow frame transfer operation
•  May be read through 1, 2, or 4 amplifiers

Documents

•  Backside package pinout for Kovar tub
•  Frontside package mechanical

Voltages

• Nomenclature explanation
• Nominal voltages for ITL/STA0500A

Amplifier

•  We have tested the devices with a 20k load

Clocking

•  Serial clocking to lower right output is S2-S3-S1-SW-OG-node
•  Serial clocking to lower left output is   S1-S3-S2-SW-OG-node
•  Serial clocking to upper right output is S2-S3-S1-SW-OG-node
•  Serial clocking to upper left output is   S1-S3-S2-SW-OG-node
•  There is one underscan serial pixel next  to each amplifier
•  Parallel clocking to the lower serial register is 3-1-2-TG
•  Parallel clocking to the upper serial register is 3-2-1-TG
•  Parallel charge shifts into S1+S2
•  Serial split is between S3 and S1 in each serial register