This document describes the backside version of the STA0520A CCD.  The device is based on a previous version of the 2688x512 CCD designed by John Geary (SAO) and fabricated by Richard Bredthauer (then at Ford/Loral).  The current version was designed by Richard Bredthauer (Semiconductor Technology Associates, Inc).

Architecture:

• 2688 columns
• 512 rows
• 15 x 15 micron square pixels
• 2 amplifiers
• MPP or normal operation
• MPP barrier phase: P3
• Split imaging area to allow frame transfer operation

Documents

• Assembly and pinout
• Package mechanical

Voltages

• Nomenclature explanation
• Nominal voltages for ITL/STA0520A

Amplifier

• We have tested the devices with a 20k load
• We measure a minimum read noise of 2.3-2.5 electrons at approximately 100 kHz.

Clocking

• Serial clocking in both registers is 3-2-1-SW-OG-node
• There are 16 underscan serial pixels next  to each amplifier.
• Parallel clocking to the lower serial register (OS2 side) is 2-1-3-TG
• Parallel clocking to the upper serial register (OS1 side) is 3-1-2--TG
• Parallel charge shifts into S2+S3

Quantum Efficiency

• Measured QE of a device optimized for 450 nm