/* UA Imaging Technology Laboratory */

/* CCD voltages file explanation for SDSU test controller */

#define OFFSET output offset on video board

#define OD output drain

#define RD reset drain

#define OTG output transfer gate

#define BIAS5 unused bias

#define BIAS6 unused bias

#define BIAS7 unused bias

#define PMULT multiplier for parallel overlap

#define PDELAY parallel overlap (ns)

==> actual parallel overlap delay is PMULT*PDELAY

#define P1HI parallel phase 1 high

#define P1LO parallel phase 1 low

#define P2HI parallel phase 2 high

#define P2LO parallel phase 2 low

#define P3HI parallel phase 3 high

#define P3LO parallel phase 3 low

#define THI transfer gate high

#define TLO transfer gate low

#define SDELAY serial clock overlap (ns)

#define S1HI serial phase 1 high

#define S1LO serial phase 1 low

#define S2HI serial phase 2 high

#define S2LO serial phase 2 low

#define S3HI serial phase 3 high

#define S3LO serial phase 3 low

#define RHI reset gate high

#define RLO reset gate low

#define SWHI summing well high

#define SWLO summing well low

#define DWELL CDS sample time (ns)