The series of steps required to optimize a sensor for backside illumination in order to improve its quantum efficiency and its range of spectral response is referred to as backside processing. This is our main area of expertise at ITL and accounts for a large fraction of our overall activities. Backside processing converts a front illuminated CCD or CMOS imaging sensor (as fabricated at a semiconductor manufacturer's foundry) into a highly optimized detector suitable for low light level imaging.
We characterize individual sensor die as well as entire lot runs at the wafer level before proceeding with backside processing. Our tests include DC shorts and opens, AC functionality, defects, CTE, and absolute gain. We perform these tests at temperatures as low as -60C.
ITL, with original funding from the National Science Foundation, has developed a cold CCD wafer probing system to quantitatively characterize scientific sensors at the wafer and die level. The goals of this system are to evaluate devices for front and back illuminated packaging, to provide rapid feedback to sensor manufacturers concerning device performance, particularly for new devices and device technologies, and to allow cryogenic and imaging characterization of other devices and device structures. We have adapted our system to handle many die and wafer sizes.
A wafer dicing saw is needed to cut (or dice) the individual detectors from the round wafers on which they are fabricated. We also dice the flip chip bonding substrates which are fabricated on silicon wafers.
Our saw has automation capabilities and can be used to dice a number of materials, including silicon, glass, and ceramics. It includes a high-conductance water-feed system which reduces static charge build-up during dicing which can lead to Electrostatic Discharge (ESD) failure of the sensitive detectors. A unique feature of our DISCO DAD3650 saw is that it has been custom fitted with an IR camera which allows dicing silicon wafers and die from the backside.
Hybridizing – Flip Chip Bonding
Our back-illuminated sensors are flip chip bonded or hybridized to mount their front side against a stable support substrate. The flip chip process also allows electrical interconnection from the sensor front side bonding pads to matching pads on the substrate. Bumps are placed on the bonding pads prior to flip chip bonding.
We have both fully automated and manual stud bumping machines to applies bumps to sensors. We use three flip chip bonding machines to align the device with the substrate and apply the necessary heat and pressure.
A important goal of our sensor optimization has been to produce a flat and stable imaging surface . The flip chip process allows this because the sensor is forced against a custom silicon support substrate. To ensure mechanical stability, we underfill epoxy between the sensor and substrate.
Silicon Sensor Etching
The heart of our sensor optimization is backside etching or thinning.
We have designed and constructed a suite of linear agitation thinning machines which move the sensor in an acid bath. Uniformity to better than one micron is obtained with this method. Etching is done in an acid mixture selective to p+ silicon. Thinning is accomplished on a die basis. We use a wax border to protect the front-side device circuitry and substrate traces from being attacked by the acid. We have successfully thinned devices as large as a 10kx10k 9-micron pixel CCD.
We use a second acid etch to remove any remaining p+ silicon and to remove stains which sometimes form on the surface. This etch is non-selective and can therefore be used to thin into the epitaxial layer to tailor device thickness, if necessary. Resolution may also be improved by ultra-thinning the device to eliminate any field-free region in the CCD. We make use of this fact to ultra-thin devices to be used in applications requiring the highest possible spatial resolution.
Thin Films Deposition and Analysis
One of the most significant quantum efficiency losses of back illuminated sensors is reflection off their back surface. The thinning process creates a mirror-like finish with an extremely high specular reflectivity. This reflection loss approaches 60% in the UV. The application of a thin film antireflection (AR) coating directly onto the sensor back surface can therefore significantly increase QE.
ITL has pioneered the development of high efficiency AR coatings for back illuminated sensors. We have found several suitable materials for silicon AR coatings, including hafnium oxide (HfO2), tantalum pentoxide (Ta2O5) and magnesium fluoride (MgF2).
For permanent backside charging, we apply a Chemisorption Coating (developed at ITL) to produce a net negative charge on the detector back surface. There is no backside damage using this process which would cause QE-temperature instabilities and/or reduce the maximum QE obtained.
Sensor Packaging and Wire Bonding
Packaging of our back illuminated CCDs is accomplished by mounting the thinned CCD with its substrate to a package. We design each silicon substrate to fit into a specific package. Each electrical trace on the substrate leads from an indium bump to a wire bonding pad. Commercial packages are often not flat enough for the large area sensors required in spectrographs and for wide field mosaics. By developing custom packages, we routinely achieve flat and stable imaging surfaces as well as provide a simpler I/O connection in the dewar.
Standard thermo compression gold ball bonding is used to wire bond from the pad to an I/O pin. To check the reliability of our wire bonds, we pull test each to the required MIL-STD specification.
We often perform a detailed measurement of a sensor’s imaging surface position after fabrication. This includes flatness as well as position relative to defined package coordinate system. Typical measurement accuracy is about two microns although much finer measurements can be made in specific cases.
We have a VIEW Summit 600 Coordinate Measuring Machine (CMM), a Zygo interferometric microscope, and other profilometry equipment to perform these measurements. Our equipment is in an ESD safe, cleanroom environment.
We have developed software and hardware systems for detector characterization, usually aimed at fully testing CCDs for scientific applications.
We also provide detector testing as a service to the community for a nominal fee. Our goal is to provide rapid feedback of device performance using well proven and calibrated techniques. All the testing is automated and script driven, requiring no operator intervention once the device is set up. We have developed an automated system using Python and LabVIEW programming for measuring quantum efficiency (QE), read noise (down to 1.0 electrons), gain, full well capacity, linearity, photoresponse non-uniformity, dark current, defect counts, and dark-current non-uniformity, and charge transfer efficiency (CTE).